1. Technical Field
The present disclosure relates to a switching power supply device, in particular, a synchronous rectifying non-insulating type switching power supply device.
2. Related Art
As a conventional insulating switching power supply device, for example, flowing inventions are proposed. WO/2000/013318-A proposes a semiconductor device that includes multiple output switching transistors having different on resistances respectively. While the multiple output switching transistors are on-operation, the transistor is turned on in order of the great to small of the on resistance. On the contrary, during off operation, the transistors are turned off in order of small to great of the on-resistance.
In addition, JP2007-252137-A proposes a non-synchronous certificating non-insulating type step-down DC-DC converter that can improve efficiency without increasing the circuit area. With decreasing the load current, an ON-period of a switching transistor is lengthened, the inductor current is decreased, and the load current is further decreased. Then, when the inductor current is decreased to the minimum current value, the voltage is increased to the output voltage, and a rectification transistor is turned off. Therefore, the inductor current stops flowing, which prevents the generation of the reverse current.
Next, example related art of the switching power supply device 100 is described below with reference to FIGS. 13 and 14. FIG. 13 is a block diagram illustrating a configuration of a related-art synchronized rectifying step-down switching power supply device 100. In FIG. 13, the switching power supply device 100 includes a high-side switch SW101 and a low-side switch SW102 connected in series between a voltage source of an input terminal Vin and a ground terminal, an inductor L10 connected between an output terminal VOUT and a junction node LX between the switches SW101 and SW102, and a capacitor C1 to smooth an output voltage at the output terminal VOUT. The switches SW101 and SW102 are, for example, metal-oxide semiconductor field-effect transistor (MOSFET). In FIG. 13, reference character lout represents the output current generated at the output terminal VOUT, Ilx represents an inductor current represents Ilx, and Vlx represents a voltage at the junction node LX. The switching power supply device 100 further includes a pulse-width modulation (PWM) control circuit 101, a dead time control circuit 102, an inverter 103, and a buffer 104 for controlling the switches SW101 and SW102. The PWM control circuit 101 outputs a signal having a duty ratio that is changed to generate the desired output voltage Vout.
A parasitic capacitance Cp101 is present between a gate and a drain of the switch SW101 and a parasitic capacitance Cp102 is present between a source and the drain of the switch SW1. Similarly, a parasitic capacitance Cp103 is present between a gate and a drain of the switch SW102, and a parasitic capacitance Cp104 is present between a source and the drain of the switch SW102.
FIG. 14 is a timing chart to illustrate the operation of the switching power supply device 100 shown in FIG. 13. Herein, output of the logic circuit is represented as high-level “H” and low level “L”. In FIG. 14, 1 cycle of the operation contains represents periods A to F. Below describes the operation of the switching power supply device shown in FIG. 13, with reference to these periods A to F shown in FIG. 14.
In FIG. 14, in the period A, the input voltage of the inverter 103 is H and an output voltage of the inverter 103 is started shifting from H to L, and an input voltage and an output voltage of the buffer 104 are kept in L state. When a gate-source voltage of the switch 101 exceeds a threshold voltage of the switch SW101, the switch 5101 is turned on, and the current starts flowing through a source-drain of the switch SW101, and the voltage Vlx at the junction node Lx is started increasing. As a result, due to the current flowing through the parasitic capacitance Cp101 between the gate and drain of the switch SW101, the output out voltage of the inverter 103 is increased, and the gate-source voltage of the switch SW101 is kept constant near a threshold value of the switch SW101. The output current of the inverter 103 for driving the switch SW1 has limited, and therefore, which can maintain a balance between the output current of the inverter 103 and the current flowing through the parasitic capacitance Cp101 of the gate and the drain of the switch SW101. At this time, the gate-source voltage of the switch SW101 is kept near the threshold voltage of the switch SW101.
In addition, due to the current flowing through the parasitic capacitance Cp103 between the gate and drain of the switch SW102, the output voltage of the buffer 104 is increased, and the gate-source voltage of the switch SW102 is increased. When a gate-source voltage of the switch SW101 exceeds a threshold voltage of the switch SW101, the current is started flowing to the switch SW102. This operation is called as a self-turn on. The current flowing through the switch SW101 contains the inductor current Ilx, and charging currents of the parasitic capacitances Cp101 to Cp104. In addition, while the switch SW102 is the self-turn on operation, the current of the switch SW101 further contains the current flowing through the switch SW102. At this time, loss expressed as a product of the drain-source current and a drain-source voltage is generated in the switch SW101.
When the voltage Vlx at the junction node LX is increased to the input voltage Vin, the process proceeds from the period A to the period B.
In the period B, the switch SW102 is off and the switch SW101 is on. At this time, in the switch SW101, a loss expressed as a product of the on-resistance of the switch SW1 and square of the inductor current Ilx is generated.
In the period C, the input voltage of the inverter 103 is changed to L, and the output voltage of the inverter 103 is transited from L to H, while the input voltage and the output voltage of the buffer 104 are kept L. When the gate-source voltage of the switch SW101 falls below a threshold voltage of the switch SW101, the switch SW101 is turned off, and the voltage Vlx at the junction node LX is started decreasing. As a result, due to the current flowing through the parasitic capacitance Cp101 between the gate and drain of the switch SW101, the output voltage of the inverter 103 is decreased, and the gate-source voltage of the switch SW101 is kept near the threshold value of the switch SW101. At this time, in the switch SW101, loss expressed as a product of the drain-source current and the drain-source voltage thereof is generated.
When the voltage Vlx at the junction ode Lx is decreased, and a voltage difference between the voltage Vlx and a ground voltage (0V) exceeds a threshold voltage of a body diode of the switch SW102, the process proceeds from the period C to the period D.
In the period D, the switches SW101 and SW102 are off. In the periods A to C, the inductor current Ilx is supplied from the switch SW101. Conversely, in the period D, when the voltage Vlx at the junction node LX exceeds a threshold voltage of the body diode of the switch SW102, the inductor Ilx is supplied from the switch SW102 instead of the switch SW101. At this time, the inductor current Ilx flows through the body diode of the switch SW102. This period is called as a dead time. At this time, in the switch SW102, a loss expressed as the product of a threshold voltage of the body diode and an inductor current Ilx is generated.
In the period E, the input voltage and the output voltage of the buffer 104 are K, while the input voltage of the inverter 103 is kept L. When the gate-source voltage of the switch SW102 exceeds the threshold voltage of the switch SW102, the switch SW102 is turned on. At this time, in the SW102, the loss expressed by the product of the on-resistance of the switch SW102 and the square of the inductor current Ilx is generated. Conversely, in the period E, the switch SW101 is kept in off state.
The length of the period D from when the switch SW101 is turned off to when the switch SW102 is turned on is controlled by the dead-time control circuit 102.
In the period F, both switches SW101 and SW102 are off. At this time, the inductor current Ilx flows through the body diode of the switch SW102. This time is called as a dead time. At this time, a loss expressed by a product of the threshold voltage of the body diode and the inductor current Ilx is generated in the switch SW102.
The loss in the periods A and C are called as “switching loss”. The product of switching loss and switching frequency means an average loss. Recently, in order to compact the members used for the switching power supply device 100, a switching frequency having equal to or greater than several MHz, is used. In the switching power supply device 100 that uses high-switching frequency, the switching frequency occupies a high rate in the total loss.
In the switching power supply device 100 shown in FIG. 13, by increasing the output current of the inverter 103 to drive the switch SW101, a slew rate is increased when the voltage Vlx at the junction node Lx is increased and decreased, thereby shortening the lengths of the periods A and C, and the switching loss is suppressed. However, in general, the MOS FET has gate resistance, delay is generated by the gate resistance, and the switching loss cannot set to zero. By contrast, when the slew rate is increased, the switch SW102 is self-turned on, and the loss caused by the current penetrating through the switches SW101 and SW102 is increased. Furthermore, as the slew rate is increased, peaks of the charge currents to the parasitic capacitances Cp101, Cp102, Cp103, and Cp104 are increased.
Due to generation of self-turn on, and increase in the peak of the charge current, the electromagnetic noise is accidentally increased. The electromagnetic noise is the external disturb to the signal during communication, malfunction in peripheral devices may occur. Accordingly, in present, although the loss is increased, it is preferable that the slew rate tend to be decreased to suppress the electromagnetic noise.
As described above, in the above-described method, the switching loss and the electromagnetic noise is a trade-off relation, as the switching frequency is increased, compacting the members in the switching power supply device and the switching power supply device itself is suppressed.